Non-volatile memory device and method of operating the same

ABSTRACT

A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

PRIORITY CLAIM

A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application No. 10-2008-0013838, filed Feb. 15, 2008, the entire contents of which are hereby incorporated by reference.

SUMMARY

The present invention generally relates to a non-volatile memory device, and more particularly, to a multi-bit non-volatile memory device and to an operational method thereof.

Multi-level non-volatile memory cells (also referred to as multi-bit non-volatile memory cells) are capable of storing two or more bits of data in each memory cell. For example, in the case of a two-bit cell, the charge storage element (pattern) of each cell is capable of being programmed into any one of four different charge states. However, highly complex peripheral circuit designs are needed to accurately program each cell into four charge states which can be reliably distinguished from one another. Circuit designs become even more complex and difficult to implement in the case of higher bit counts in which five or more distinguishable charge states must be programmed.

Embodiments of the present invention provide a non-volatile memory device that includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin, the protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

In various embodiments, the channel region includes a top wall extending between the first and second sidewalls, each of the first and second control gates partially extending over the top wall of the channel regions. Also, the first charge storage pattern extends between the top wall of the channel region and the first control gate, and the second charge storage pattern extends between the top wall of the channel region and the second control gate. The channel region is recessed relative to the source and drain regions.

In various embodiments, the non-volatile memory device further includes a first word line connected to the first control gate and a second word line connected to the second control gate.

In various embodiments, the non-volatile memory device further includes a tunneling insulation layer between each of the first and second charge storage patterns and the first and second sidewalls of the channel region, respectively. Also, the non-volatile memory device further includes a blocking insulation layer between each of the first and second charge storage patterns and the first and second control gates, respectively.

Embodiments of the present invention provide a data programming method of a non-volatile memory device. The method includes storing a charge in a first charge storage pattern or a second charge storage pattern by applying a programming electric field between a semiconductor substrate and a first control gate or between the semiconductor substrate and a second control gate, respectively.

Embodiments of the present invention provide a data erasing method of a non-volatile memory device. The method includes erasing charges stored in a first charge storage pattern and a second charge storage pattern by applying an erase electric field between a semiconductor substrate and first and second control gates, respectively.

Embodiments of the present invention provide a data reading method of a non-volatile memory device. The method includes sensing a drain current by applying a reference voltage to a source region, applying a drain read voltage to a drain region, and applying a gate read voltage to a first control gate; and sensing the drain current by applying a reference voltage to the source region, applying a drain read voltage to the drain region, and applying a gate read voltage to a second control gate.

BRIEF DESCRIPTION OF THE FIGURES

The attached drawings illustrate exemplary and non-limiting embodiments of the present invention, in which:

FIG. 1 is a block diagram illustrating a layout of a cell array of a non-volatile memory device, according to an embodiment of the present invention;

FIG. 2 is a partially cut-away perspective view illustrating a non-volatile memory cell of FIG. 1, according to an embodiment of the present invention;

FIG. 3 shows cross-sectional views taken along lines X-X′ and Y-Y′, respectively, of FIG. 2, according to an embodiment of the present invention;

FIGS. 4A through 4F are perspective views for describing a method of fabricating a non-volatile memory device, according to an embodiment of the present invention;

FIGS. 5A through 5F are cross-sectional views taken along lines X-X′ and Y-Y′ of FIGS. 4A through 4F, respectively, according to an embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram illustrating a non-volatile memory cell of FIGS. 2 and 3, according to an embodiment of the present invention;

FIG. 7A a graph illustrating charges of charge storage patterns relative to program times during a programming operation of a non-volatile memory cell, according to an embodiment of the present invention;

FIG. 7B is a graph illustrating F-N currents relative to a program times during a programming operation of a non-volatile memory cell, according to an embodiment of the present invention;

FIG. 8 is a graph illustrating charges of charge storage patterns of a non-volatile memory cell based on program biases, according to an embodiment of the present invention;

FIG. 9 is a graph illustrating drain currents based on gate voltages of a non-volatile memory cell, according to one embodiment of the present invention;

FIG. 10A is a graph illustrating charges of charge storage patterns relative to erase times during an erasing operation of a non-volatile memory cell, according to an embodiment of the present invention;

FIG. 10B is a graph illustrating F-N currents relative to erase times during an erasing operation of a non-volatile memory cell, according to an embodiment of the present invention;

FIG. 11A is a graph illustrating charges of charge storage patterns relative to program times during a programming operation of a non-volatile memory cell, according to an embodiment of the present invention;

FIG. 11B is a graph illustrating F-N currents relative to program times during a programming operation of a non-volatile memory cell, according to an embodiment of the present invention; and

FIG. 12 is a graph illustrating drain currents based on gate voltages after performing a programming operation of a non-volatile memory cell, according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Rather, these embodiments are provided as examples, to convey the concept of the invention to one skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments of the present invention. Throughout the drawings and written description, like reference numerals will be used to refer to like or similar elements. Further, the dimensions of layers and regions are exaggerated for clarity of illustration.

FIG. 1 is a block diagram showing a cell array layout of a non-volatile memory device, according to an illustrative embodiment of the present invention.

Referring to FIG. 1, active pins 10 a, defined by a device isolation layer formed in a semiconductor substrate, are arranged laterally in one direction. A string selection line SSL and a ground selection line GSL cross over the active pins 10 a. Further, in the representative cell array layout, multiple word line pairs WL_(00U)-WL_(00L), WL_(01U)-WL_(01L), . . . , WL_(NU)-WL_(NL) cross over the active pins 10 a between the string selection line SSL and the ground selection line GSL. The word lines WL_(00U) . . . WL_(NU) are referred to as first word lines, and the word lines WL_(00P) . . . WL_(NP) are referred to second word lines.

Pairs of gate patterns G1 and G2 are arranged spaced apart from each other and located between the active pin 10 a and the pair of word lines WL_(NU)-WL_(NL). The gate patterns G1 and G2 overlap opposite sidewalls of the active pin 10 a, respectively, and extend over the top of the active pin 10 a. Accordingly, at least a portion of the top of the active pin 10 a may be exposed between the pair of gate patterns G1 and G2.

In the cell array, the first word lines WL_(00U), WL_(01U), . . . , WL_(NU) are electrically connected to the first gate patterns G1 through first contacts 70 a, which may overlap one sidewall of the respective active pin 10 a. The second word lines WL_(00L), WL_(01L), . . . , WL_(NL) are electrically connected to the second gate patterns G2 through second contacts 70 b, which may overlap the other sidewall of the respective active pin 10 a.

Bit lines (not shown) may be located on the word line pairs WL_(00U)-WL_(00L), WL_(01U)-WL_(01L), . . . , WL_(NU)-WL_(NL), and may be parallel to the active pins 10 a. In an embodiment, the bit lines respectively contact the active pins 10 a through third contacts 70 c.

FIG. 2 is a partially cut-away perspective view showing a non-volatile memory cell of FIG. 1, according to an illustrative embodiment of the present invention. FIG. 3 shows cross-sectional views taken along lines X-X′ and Y-Y′, respectively, of FIG. 2, according to an illustrative embodiment of the present invention. Illustrations of word lines and device isolation layers are omitted from FIGS. 2 and 3 for convenience of description.

Referring to FIGS. 2 and 3, a semiconductor substrate 10 includes a base region 10 b and an active pin 10 a protruding from the base region 10 b. The active pin 10 a includes a source region 10 as, a drain region 10 ad, and a channel region 10 ac located between the source/drain regions 10 as and 10 ad. A source impurity region 11 s and a drain impurity region 11 d are located in the source/drain regions 10 as and 10 ad, respectively. The source/drain impurity regions 11 s and 11 d may each include a high concentration impurity region and a low concentration impurity region.

The channel region 10 ac is more recessed than the source/drain regions 10 as and 10 ad. The sum of the length of the channel region 10 ac and height differences between the top of the channel region 10 ac and the respective tops of the source/drain regions 10 as and 10 ad is defined as channel length L_(CH). Accordingly, the channel length L_(CH) is greater than that of a typical flat transistor, thus suppressing a short channel effect.

A first control gate 61 is located on a first sidewall (i.e., one sidewall) of the channel region 10 ac. A charge storage pattern 41 is located between the first control gate 61 and the first side wall. The first control gate 61 may extend along a portion of the top of the channel region 10 ac. At least a portion of the first charge storage pattern 41 extends between the top of the channel region 10 ac and the first control gate 61.

A second control gate 62 is located on a second side wall (i.e., another sidewall) of the channel region 10 ac. The second control gate 62 is separated from the first control gate 61 by a predetermined distance. A second charge storage pattern 42 is located between the second control gate 62 and the second sidewall. The second charge storage pattern 42 is electrically isolated from the first charge storage pattern 41. The second control gate 62 may extend along another portion of the top of the channel region 10 ac. At least a portion of the second charge storage pattern 42 extends between the top of the channel region 10 ac and the second control gate 62.

Each of the charge storage patterns 41 and 42, respectively arranged on sidewalls of the channel region 10 ac, may have a charge state “0” or “1.” That is, each of the charge storage patterns 41 and 42 is configured to store one bit individually. Accordingly, because two bits can be stored in a unit cell, twice as much information can be stored as compared to a one-bit unit cell, and programming error can be reduced compared to when four charge states are stored in a one charge storage pattern.

However, the charge storage patterns 41 and 42 are not limited to the above description. Each may have charge states of “00,” “01,” “10” and “11,” individually. That is, each of the charge storage patterns 41 and 42 may store two bits. Therefore, a total of four bits can be stored in the unit cell.

Additionally, because the charge storage patterns 41 and 42 and the control gates 61 and 62 extend to the sidewalls and the top of the channel region 10 ac, channel widths W_(CH1) and W_(CH2) are greater than those of a typical flat transistor, thus suppressing narrow width effect. Consequently, current driving capability is improved and distribution of a threshold voltage is reduced.

A tunnel insulation layer 30 is located between the charge storage patterns 41 and 42 and the channel region 10 ac. A blocking insulation layer 50 is located between the charge storage pattern 41 and 42 and the control gates 61 and 62. The tunnel insulation layer 30 and the blocking insulation layer 50 may be a silicon oxide layer, and the tunnel insulation layer 30 may be a thermal oxide layer, for example.

Each of the control gates 61 and 62 may be a stacked layer of polysilicon layers, or a polysilicon layer and a metal silicide layer, for example. Also, the metal silicide layer may be a tungsten silicide layer, a cobalt silicide layer, or a nickel silicide layer, for example.

The charge storage patterns 41 and 42 may be a charge trap layer, a floating gate, or an insulation layer including a conductive nano crystal, for example. More particularly, the charge trap layer may be a silicon nitride layer, and the floating gate may be a poly silicon layer, and the conductive nano crystal may be a silicon nano crystal or a metal nano crystal. When the charge storage patterns 41 and 42 are a charge trap layer or an insulation layer including a conductive nano crystal, the blocking insulation layer 50 may be omitted.

FIGS. 4A through 4F are perspective views showing a method of fabricating a non-volatile memory device, according to an illustrative embodiment of the present invention. FIGS. 5A through 5F are cross-sectional views taken along lines X-X′ and Y-Y′ of FIGS. 4A through 4F, according to an illustrative embodiment of the present invention.

Referring to FIGS. 4A and 5A, an active pin 10 a is defined by a device isolation trench 10 t formed in semiconductor substrate 10. The active pin 10 a protrudes from a base region 10 b corresponding to a bottom portion of the device isolation trench 10 t. The active pin 10 a includes a source region 10 as, a drain region 10 ad and a channel region 10 ac between the source and drain regions 10 as and 10 ad.

A first insulation liner (not shown) may be formed on an inner wall of the device isolation trench 10 t. The first insulation liner may be a thermal oxide layer, for example, formed by thermal-oxidizing the inner wall of the device isolation trench 10 t. The first insulation liner effectively repairs etching damage of the inner wall of the device isolation trench 10 t, caused during formation of the isolation trench 10 t. A second insulation liner (not shown) may be formed on the first insulation liner. The second insulation liner may be a silicon nitride layer, for example.

After the insulation liners filling the device isolation trench 10 t are formed on the semiconductor substrate 10, a resulting device isolation insulation layer is planar-etched until the top of the active pattern 10 a is exposed in order to form device isolation layer 15. The planar-etching of the device isolation insulation layer can be completed, for example, through a chemical-mechanical polishing (CMP) method. Also, the device isolation layer 15 may be a silicon oxide layer, for example, such as a high density plasma (HDP) oxide.

Referring to FIGS. 4B and 5B, an etching mask layer is formed on the active pin 10 a and the device isolation layer 15, and an etching mask pattern 17, defining a slit 17 a, is formed by patterning the etching mask layer. The slit 17 a crosses over the top of the channel region 10 ac. The etching mask pattern 17 may be formed by a layer having an etching selectivity with respect to the active pin 10 a and the device isolation layer 15. The etching mask pattern 17 may be formed of a silicon nitride layer, for example.

By using the etching mask pattern 17 as a mask to etch a top portion of the device isolation layer 15 exposed through the slit 17 a, a groove 15 a is formed, exposing sidewalls of the channel region 10 ac. The groove 15 a may be formed through an anisotropic etching method, for example, using an etch recipe for selectively removing the device isolation layer 15 (i.e., having an etching selectivity with respect to the active pin 10 a and the etching mask pattern 17).

Referring to FIGS. 4C and 5C, use of the etching mask pattern 17 results in recessing the top region of the channel region 10 ac exposed through the slit 17 a. Consequently, a channel recess CR is formed on the recessed channel region 10 ac. When recessing of the channel region 10 ac, the recess amount is adjusted so that the top of the recessed channel region 10 ac is higher than the bottom of the groove 15 a. The recessing of the channel region 10 ac may be completed through an anisotropic etching method, for example, using an etch recipe that does not etch the device isolation layer 15 and the etching mask pattern 17, but selectively etches the channel region 10 ac.

Referring to FIGS. 4D and 5D, the tops of the source/drain regions 10 as and 10 ad, and the top of the device isolation layer 15 are exposed by removing the etching mask pattern 17. A height difference S1 between the bottom of the groove 15 a and the top of the recessed channel region 10 ac factors in determining the channel widths W_(CH1) and W_(CH2) of a transistor. Furthermore, a height difference S2 between the top of the recessed channel region 10 ac and the tops of the source/drain regions 10 as and 10 ad factors in determining the channel length L_(CH).

Referring to FIGS. 4E and 5E, a tunnel insulation layer 30 is formed where the etching mask pattern 17 has been removed. The tunnel insulation layer 30 may be a silicon oxide layer, for example. Furthermore, the tunnel insulation layer 30 may be a thermal oxide layer formed by thermal-oxidizing the active pin 10 a.

A charge storage layer 40, a blocking insulation layer 50 and a control gate electrode layer 60 are sequentially formed on the semiconductor substrate 10 having the tunnel insulation layer 30. For example, the charge storage layer 40 may be a charge trap layer, a floating gate layer, or an insulation layer including a conductive nano crystal, and the blocking insulation layer 50 may be a silicon oxide layer. When the charge storage layer 40 is a charge trap layer or an insulation layer including the conductive nano crystal, the blocking insulation layer 50 may be omitted. The control gate electrode layer 60 is formed having a thickness that sufficiently fills the groove 15 a and the channel recess CR.

A preliminary gate pattern PG is formed by sequentially patterning the control gate electrode layer 60, the blocking insulation layer 50, the charge storage layer 40 and the tunnel insulation layer 30. The preliminary gate pattern PG covers the sidewalls and the tops of the channel region 10 ac and fills the groove 15 a.

Through ion implantation IP using the preliminary gate pattern PG as a mask, source/drain impurity regions 11 s and 11 d are respectively formed in the source/drain regions 10 as and 10 ad. The source/drain impurity regions 11 s and 11 d may include a low concentration impurity region (not shown) and a high concentration impurity region (not shown), respectively. In this case, after forming the low concentration impurity region through low concentration ion implantation using the preliminary gate pattern PG as a mask, high concentration ion implantation is performed after forming spacers (not shown) on the sidewalls of the preliminary gate pattern PG, such that high concentration impurity region can be formed.

Referring to FIGS. 4F and 5F, first gate pattern G1 and second gate pattern G2 are formed, separated from one another, by partially removing the gate pattern PG on the top of the channel region 10 ac. The first gate pattern G1 is located on one side wall of the channel region 10 ac, i.e., a first sidewall, and extends over a portion of the top of the channel region 10 ac. The second gate pattern G2 is located on another sidewall of the channel region 10 ac, i.e., a second sidewall, and extends over another portion of the top of the channel region 10 ac.

The first gate pattern G1 includes sequentially-stacked tunnel insulation layer 30, first charge storage pattern 41, blocking insulation layer 50 and first control gate 61. The second gate pattern G2 includes sequentially-stacked tunnel insulation layer 30, second charge storage pattern 42, blocking insulation layer 50 and second control gate 62.

Hereinafter, methods of operating a non-volatile memory device, according to illustrative embodiments of the present invention, will be described.

FIG. 6 is an equivalent circuit diagram of a non-volatile memory cell of FIGS. 2 and 3, according to an illustrative embodiment of the present invention. Table 1 below represents an operational condition of a device according to an embodiment of the present invention.

TABLE 1 V_(CG1) V_(CG2) Vd Vs Vw CS41 CS42 Program Vpg GND — — GND P — GND Vpg — — GND — P Erase Ver Ver — — GND — — Read Vcg.read GND Vd.read GND GND GND Vcg.read Vd.read GND GND

Representative data programming, reading and erasing methods will be described below with reference to FIG. 6 and Table 1.

With respect to a method for programming data, a programming electric field is applied between the first control gate 61 and the substrate. For example, positive program voltage V_(pg) is applied to the first control gate 61, ground voltage GND is applied to the second control gate 62 and the substrate, and source/drain impurity regions 11 s and 11 d are made floating. As a result, the non-volatile memory cell is programmed by storing an electron in the first charge storage pattern 41 through Fowler-Nordheim (F-N) tunneling.

At the same or a different time, a programming electric field is applied between the second control gate 62 and the substrate. For example, positive program voltage V_(pg) is applied to the second control gate 62, ground voltage GND is applied to the first control gate 61 and the substrate, and source/drain impurity regions 11 s and 11 d are made floating. As a result, the non-volatile memory cell is programmed by storing an electron in the second charge storage pattern 42 through F-N tunneling. In an embodiment, the program voltage V_(pg) may be between about 9 V and about 12 V.

Accordingly, the non-volatile memory cell has four levels to store two-bit data. The four levels include state “11” (when no electrons are stored in the first and second charge storage patterns 41 and 42), state “01” (when an electron is stored in only the first charge storage pattern 41), state “10” (when an electron is stored in only the second charge storage pattern 42), and state “00” (when electrons are stored in both the first and second charge storage patterns 41 and 42).

With respect to a method for reading data, gate read voltage Vcg.read is applied to the first control gate 61, drain read voltage Vd.drain is applied to the drain region 11 d, and ground voltage GND is applied to the source region 11 s and the substrate. During this state, it is determined whether an electron is stored in the first charge storage pattern 41 by sensing a drain current.

Then, gate read voltage Vcg.read is applied to the second control gate 62, drain read voltage Vd.drain is applied to the drain region 11 d, and ground voltage GND is applied to the source region 11 s and the substrate. It is then determined whether an electron is stored in the second charge storage pattern 42 by sensing the drain current.

By combining a determination result of whether an electron is stored in the first charge storage pattern 41 and a determination result of whether an electron is stored in the second charge storage pattern 42, a charge state of the four possible levels of the non-volatile memory cell can be read.

With respect to a method for erasing data, an erase electric field is applied between the first and second control gates 61 and 62 and the substrate. For example, in the depicted embodiment, negative erase voltage Ver is applied to the first and second control gates 61 and 62, ground voltage GND is applied to the substrate, and the source/drain impurity regions 11 s and 11 d are made floating. As a result, electrons stored in the first and second charge storage patterns 41 and 42 are erased through F-N tunneling.

FIG. 7A a graph showing charges of charge storage patterns in relation to program times during a programming operation of a non-volatile memory cell, according to an illustrative embodiment of the present invention. FIG. 7B is a graph illustrating F-N currents in relation to program times during a programming operation of a non-volatile memory cell, according to an illustrative embodiment of the present invention.

Referring to FIGS. 7A and 7B, when voltage Vcg1 applied to the first control gate 61 is set with a program voltage of about 12 V, and voltage Vcg2 applied to the second control gate 62 is set with a ground voltage during a programming operation, charges of about −8.5×10⁻¹⁶ C/cm are stored in the first charge storage pattern 41 and no charge is stored in the second charge storage pattern 42. Additionally, because an F-N current is measured during the storing of charges, the storing of the charges may occur through F-N tunneling.

FIG. 8 is a graph showing charges of charge storage patterns of a non-volatile memory cell in relation to program biases, according to an illustrative embodiment of the present invention.

Referring to FIG. 8, when voltage Vcg1 applied to the first control gate 61 is set with a program voltage of about 12 V, and voltage Vcg2 applied to the second control gate 62 is set with a ground voltage during a programming operation, charges of about −8.5×10⁻¹⁶ C/cm are stored in the first charge storage pattern 41 and no charge is stored in the second charge storage pattern 42 (indicated by •). In comparison, when voltage Vcg2 applied to the second control gate 62 is set with a program voltage of about 12 V and voltage Vcg1 applied to the first control gate 61 is set with a ground voltage during a programming operation, charges of about −8.5×10⁻¹⁶ C/cm are stored in the second charge storage pattern 42 and no charge is stored in the first charge storage pattern 41 (indicated by ▪).

FIG. 9 is a graph showing drain currents in relation to gate voltages of a non-volatile memory cell, according to an illustrative embodiment of the present invention.

Referring to FIG. 9, a threshold voltage of a non-volatile memory cell is about 0.8 V before programming, about 4.5 V in a programmed state (storing an electron (data) in one side of a charge storage pattern), and about 1 V when the stored data are erased. Therefore, when a read voltage (e.g., about 3.5 V) is applied to the first control gate 61 during a read operation, it can be determined whether there is an electron stored in the first charge storage pattern 41. In particular, when the first charge storage pattern 41 is in a programmed state (indicated by •), it may not be turned on at a voltage of about 3.5 V, and when the first charge storage pattern 41 is in a state before programming (indicated by ▪) or in a state after erasing (indicated by ▴), it may be turned on at a voltage of about 3.5 V.

FIG. 10A is a graph illustrating charges of charge storage patterns in relation to erase times during an erasing operation of a non-volatile memory cell, according to an illustrative embodiment of the present invention. FIG. 10B is a graph illustrating F-N currents in relation to erase times during an erasing operation of a non-volatile memory cell, according to an illustrative embodiment of the present invention.

Referring to FIG. 10A, when voltage Vcg1 applied to the first control gate 61 is set with an erase voltage of about −9 V and voltage Vcg2 applied to the second control gate 62 is set with a ground voltage during an erasing operation, charges of about −8.0×10⁻¹⁶ C/cm stored in the first charge storage pattern 41 are erased. However, there is no change in the charge amount stored in the second charge storage pattern 42.

Referring to FIG. 10B, since an F-N current is measured during the erasing of charges, it is apparent that charge storing may occur through F-N tunneling.

Table 2 represents another operational condition of a non-volatile memory device according to an illustrative embodiment of the present invention.

TABLE 2 V_(CG1) V_(CG2) Vd Vs Vw CS41 CS42 Program Vpg1, GND — — GND P1, — Vpg2, or P2, Vpg3 or P3 GND Vpg1, — — GND — P1, Vpg2, or P2, Vpg3 or P3 Erase Ver Ver — — GND — — Read Vcg.read1 GND Vd.read GND GND Vcg.read2 GND Vd.read GND GND Vcg.read3 GND Vd.read GND GND GND Vcg.read1 Vd.read GND GND GND Vcg.read2 Vd.read GND GND GND Vcg.read3 Vd.read GND GND

Representative data programming, reading and erasing methods will be described below with reference to FIG. 6 and Table 2.

With respect to a method for programming data, one of first, second or third programming electric fields having respectively different amplitudes is applied between the first control gate 61 and the semiconductor substrate. For example, in an embodiment, one of first, second or third program voltages Vpg1, Vpg2 and Vpg3 is applied to the first control gate 61, ground voltage GND is applied to the second control gate 62 and the substrate, and the source/drain impurity regions 11 s and 11 d are made floating. The first to third program voltages Vpg1, Vpg2 and Vpg3 may be 9 V, 10 V and 12 V, respectively. Accordingly, an electron is stored in the first charge storage pattern 41 through F-N tunneling. The number of electrons stored in the first charge storage pattern 41 may vary (e.g., P1, P2 or P3) according to the amplitude of a program voltage applied to the first control gate 61. Accordingly, the first charge storage pattern 41 can have any one of four levels (states “00,” “01,” “10” and “11”) after a programming operation or no operation is performed.

At the same or a different time, one of the first to third programming electric fields having different amplitudes is applied between the second control gate 62 and the semiconductor substrate. For example, in an embodiment, one of the first to third program voltages Vpg1, Vpg2 and Vpg3 is applied to the second control gate 62, ground voltage GND is applied to the first control gate 61 and the semiconductor substrate, and the source/drain impurity regions 11 s and 11 d are made floating. The first to third program voltages Vpg1, Vpg2 and Vpg3 may be 9 V, 10 V and 12 V, respectively. Accordingly, an electron is stored in the second charge storage pattern 42 through F-N tunneling. The number of electrons stored in the second charge storage pattern 42 may vary (e.g., P1, P2 or P3) according to the amplitude of a program voltage applied to the second control gate 62. Accordingly, the second charge storage pattern 42 can have any one of four levels (states “00,” “01,” “10” and “11”) after a programming operation or no operation is performed.

By combining charge states of the first and second charge storage patterns 41 and 42, the non-volatile memory cell has 16 levels of charge states, and is able to store four-bit data.

With respect to a method for reading data, when drain read voltage Vd.read is applied to the drain region 11 d and ground voltage GND is applied to the second control gate 62, the source region 11 s and the substrate, first, second and third gate read voltages Vcg.read1, Vcg.read2 and Vcg.read3, having different amplitudes, respectively, are sequentially applied to the first control gate 61. For example, in an embodiment, the first to third gate read voltages Vcg.read1, Vcg.read2 and Vcg.read3 may be 4.5 V, 3.5 V and 2 V, respectively. A charge state stored in the first charge storage pattern 41 can be determined when a drain current is measured for each voltage.

Next, when drain read voltage Vd.read is applied to the drain region 11 d and ground voltage GND is applied to the first control gate 61, the source region 11 s and the substrate, first to third gate read voltages Vcg.read1, Vcg.read2 and Vcg.read3 are sequentially applied to the second control gate 62. For example, in an embodiment, the first to third gate read voltages Vcg.read1, Vcg.read2 and Vcg.read3 may be about 4.5 V, about 3.5 V and about 2 V, respectively. A charge state stored in the second charge storage pattern 42 can be determined when a drain current is measured for each voltage.

The method for erasing data with respect to the embodiment illustrated in Table 2 is substantially the same as the method for erasing data discussed above with respect to the embodiment illustrated in Table 1. Therefore, the description of this method will not be repeated.

FIG. 11A is a graph showing charges of charge storage patterns in relation to program times during a programming operation of a non-volatile memory cell, according to an illustrative embodiment of the present invention. FIG. 11B is a graph illustrating F-N currents in relation to program times during a programming operation of a non-volatile memory cell, according to an illustrative embodiment of the present invention.

Referring to FIG. 11A, when voltage Vcg1 applied to the first control gate 61 is set with a first program voltage of about 10 V, charges of about −4.2×10⁻¹⁶ C/cm are stored in the first charge storage pattern 41 (state “10”). When voltage Vcg1 applied to the first control gate 61 is set with a second program voltage of about 11 V, charges of about −6.4×10⁻¹⁶ C/cm are stored in the first charge storage pattern 41 (state “01”). When voltage Vcg1 applied to the first control gate 61 is set with a third program voltage of about 12 V, charges of about −8.6×10⁻¹⁶ C/cm are stored in the first charge storage pattern 41 (state “00”). When the first charge storage pattern 41 is not programmed, no charge is stored in the first charge storage pattern 41 (state “11”). Accordingly, each of the charge storage patterns of the non-volatile memory cell according to embodiments of the present invention may have a charge state of one of four distinguishable levels. As a result, when combining charge states of the first and second charge storage patterns 41 and 42, the non-volatile memory cell can have 16 levels of charge states, and thus the non-volatile memory cell is able to store four-bit data.

Referring to FIG. 11B, since an F-N current is measured during charge storing, it is apparent that this charge storing may occur through F-N tunneling.

FIG. 12 is a graph showing drain currents in relation to gate voltages after performing a programming operation, according to an illustrative embodiment of the present invention.

Referring to FIG. 12, a threshold voltage of a non-volatile memory cell is about 1 V in state “11,” about 2.7 V in state “10,” about 3.7 V in state “01” and about 4.7 V in state “00.” Accordingly, when read voltages (e.g., voltages of about 2 V, about 3.3 V and about 4.3 V) are sequentially applied to the first control gate 61, charge states stored in the first charge storage pattern 41 can be determined. More particularly, when the first charge storage pattern 41 is in state “11,” it is turned on at all read voltages. When the first charge storage pattern 41 is in state “10,” it is turned on at a voltage of about 3.3 V or about 4.3 V. When the first charge storage pattern 41 is in state “01,” it is turned on at only a voltage of about 3.3 V. When the first charge storage pattern 41 is in state “11,” it is turned on at only a voltage of about 4.3 V. Therefore, charge states corresponding to four levels in each charge storage pattern of a non-volatile memory cell can be stably read.

According to one or more embodiments of the present invention, respectively separated charge storage patterns on sidewalls of a channel region can have two levels of independent charge states. Because each charge storage pattern stores a one-bit individually, the unit cell can store a two-bit. Accordingly, the unit cell stores twice the information as compared to a unit cell storing only a one-bit. Further, programming errors can be reduced as compared to storing four charge states in one charge storage pattern.

Additionally, a channel region is more recessed as compared to source/drain regions. Therefore, the channel length of the channel region is increased as compared to a typical flat transistor, suppressing short channel effect. Likewise, since charge storage patterns and control gates extend to the sidewalls of the channel region and the top of the channel region, the channel width is increased as compared to a typical flat transistor, suppressing short width effect.

While the present invention has been shown and described in connection with exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. 

What is claimed is:
 1. A non-volatile memory device comprising: a semiconductor substrate including a protruding active pin, the active pin comprising source and drain regions and a channel region located between the source and drain regions; a first control gate on a first sidewall of the channel region; a second control gate on a second sidewall of the channel region, the second control gate being separated from the first control gate; a first charge storage pattern between the first sidewall and the first control gate; and a second charge storage pattern between the second sidewall and the second control gate, wherein the second charge storage pattern is electrically isolated from the first charge storage pattern.
 2. The non-volatile memory device of claim 1, wherein the channel region comprises a top wall extending between the first and second sidewalls, each of the first and second control gates partially extending over the top wall of the channel regions; and wherein the first charge storage pattern extends between the top wall of the channel region and the first control gate, and the second charge storage pattern extends between the top wall of the channel region and the second control gate.
 3. The non-volatile memory device of claim 1, wherein the channel region is recessed relative to the source and drain regions.
 4. The non-volatile memory device of claim 1, further comprising: a first word line connected to the first control gate and a second word line connected to the second control gate.
 5. The non-volatile memory device of claim 1, further comprising: a tunneling insulation layer between each of the first and second charge storage patterns and the first and second sidewalls of the channel region, respectively; and a blocking insulation layer between each of the first and second charge storage patterns and the first and second control gates, respectively. 